1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method for fabricating a semiconductor device, in which, when a MOSFET, a capacitor, and a resistor which are elements for an analog integrated circuit (IC) are fabricated using a polycide and salicide process, electrodes of a capacitor are formed of polycide to minimize a resistance of the electrodes and to give a symmetry to the electrode, thus advancing the performance of the device.
2. Discussion of the Related Art
A conventional method for fabricating a semiconductor device will be described below with reference to the accompanying drawings.
FIGS. 1a to 1d are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
Referring initially to FIG. 1a, a field oxide layers 12 is formed on a predetermined area of a semiconductor device 11 to define an active region. Subsequently, a gate insulating layer 12a is grown on the entire surface of the semiconductor substrate 11 including the field oxide layer 12. A polysilicon layer 13, which is used as a lower electrode of a capacitor, is formed on the gate insulating layer 12a including the field oxide layer 12 and then a metal layer is formed thereon. Next, an annealing process is performed to form a polycide layer 14 at interface of the polysilicon layer and the metal layer. Subsequently, a dielectric layer 15 and a polysilicon layer 16, which is used as an upper electrode of the capacitor, are successively formed on the polycide layer 14.
Referring to FIG. 1b, a first photo resist film 17 is formed on the polysilicon layer 16 and then patterned by an exposure and to development process. Using the photo resist pattern 17 as a mask, the polysilicon layer 16 and the dielectric layer 15 are selectively removed by an etching process to form an upper electrode 16a of the capacitor.
Referring to FIG. 1c, the remaining photo resist film 17 is removed, and then a second photo resist film 18 is coated on the polysilicon layer including the upper electrode 16a and patterned by an exposure and development process so that the second photo resist film is remained enough to cover the dielectric layer 15 and the upper electrode 16a.
Referring to FIG. 1d, using the second photo resist pattern 18 as a mask, the polycide layer 14 and the polysilicon layer 13 are successively removed to form a lower electrode 13a. Next, a polysilicon for a resistor pattern is formed on the semiconductor substrate 11 including the upper electrode 16a of the capacitor and then is selectively removed to form a resistor pattern 19 made of polysilicon on a predetermined area of the field oxide layer 12. A gate electrode 20 is formed on the semiconductor substrate 11 of the active region. Accordingly, there are formed the lower electrode made of polycide and the upper electrode made of polysilicon. And the gate electrode and the resistor pattern 19 are made of polysilicon.
The conventional method for fabricating a semiconductor device has the following problems.
First, a MOSFET, a capacitor, and a resistor, which are elements constituting an analog IC, are formed by respective processes and therefore the overall process is complex.
Second, since the material of a resistor used as a resistance and the material of electrodes of a capacitor are all made of polysilicon, the resistance of the electrode of a capacitor is increased, thereby increasing the delay of signals and power loss.